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10/06/08 www.irf.com 1 hexfet power mosfet benefits improved gate, avalanche and dynamic dv/dt ruggedness fully characterized capacitance and avalanche soa enhanced body diode dv/dt and di/dt capability lead-free applications high efficiency synchronous rectification in smps uninterruptible power supply high speed power switching hard switched and high frequency circuits s d g 96187 irfs3006-7ppbf gds gate drain source v dss 60v r ds ( on ) typ. 1.5m max. 2.1m i d ( silicon limited ) 293a i d ( packa g e limited ) 240a absolute maximum ratings symbol parameter units i d @ t c = 25c continuous drain current, v gs @ 10v (silicon limited) i d @ t c = 100c continuous drain current, v gs @ 10v (silicon limited) i d @ t c = 25c continuous drain current, v gs @ 10v (package limited) i dm pulsed drain current p d @t c = 25c maximum power dissipation w linear derating factor w/c v gs gate-to-source voltage v dv/dt peak diode recovery v/ns t j operating junction and t stg storage temperature range soldering temperature, for 10 seconds (1.6mm from case) mounting torque, 6-32 or m3 screw avalanche characteristics e as (thermally limited) sin g le pulse avalanche ener g y mj i ar avalanche current a e ar repetitive avalanche ener g y mj thermal resistance symbol parameter typ. max. units r jc junction-to-case CCC 0.4 r ja junction-to-ambient (pcb mount) CCC 40 -55 to + 175 20 2.5 10lb in (1.1n m) max. 293 207 1172 240 c a c/w 300303 see fig. 14, 15, 22a, 22b, 375 11 downloaded from: http:///

2 www.irf.com s d g pulse width 400s; duty cycle 2%. c oss eff. (tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss . c oss eff. (er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 to 80% v dss . when mounted on 1" square pcb (fr-4 or g-10 material). for recommended footprint and soldering techniquea refer to applocation note # an-994 echniques refer to application note #an-994.

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calcuted continuous current based on maximum allowable junction temperature bond wire current limit is 240a. note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. repetitive rating; pulse width limited by max. junction temperature. limited by t jmax , starting t j = 25c, l = 0.021mh r g = 25 ? , i as = 168a, v gs =10v. part not recommended for use above this value . i sd 168a, di/dt 1410 a/s, v dd v (br)dss , t j 175c. static @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. unit s v (br)dss drain-to-source breakdown volta g e 60 CCC CCC v ? v (br)dss / ? t j breakdown volta g e temp. coefficient CCC 0.07 CCC v/c r ds(on) static drain-to-source on-resistance CCC 1.5 2.1 m ? v gs(th) gate threshold volta g e 2.0 CCC 4.0 v i dss drain-to-source leaka g e current CCC CCC 20 CCC CCC 250 i gss gate-to-source forward leaka g e CCC CCC 100 gate-to-source reverse leaka g e CCC CCC -100 r g(int) internal gate resistance CCC 2.1 CCC ? dynamic @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. unit s g fs forward transconductance 290 CCC CCC s q g total gate char g e CCC 200 300 q gs gate-to-source char g e CCC 37 CCC q gd gate-to-drain ("miller") char g e CCC 60 CCC q sync total gate char g e sync. (q g - q gd ) CCC 140 CCC t d(on) turn-on delay time CCC 14 CCC t r rise time CCC 61 CCC t d(off) turn-off delay time CCC 118 CCC t f fall time CCC 69 CCC c iss input capacitance CCC 8850 CCC c oss output capacitance CCC 1007 CCC c rss reverse transfer capacitance CCC 525 CCC c oss eff. (er) effective output capacitance (energy related) CCC 1460 CCC c oss eff. (tr) effective output capacitance (time related) CCC 1915 CCC diode characteristics symbol parameter min. typ. max. unit s i s continuous source current (body diode) i sm pulsed source current (body diode) v sd diode forward volta g e CCC CCC 1.3 v t rr reverse recovery time CCC 44 CCC t j = 25c v r = 51v, CCC 48 CCC t j = 125c i f = 168a q rr reverse recovery char g e CCC 51 CCC t j = 25c di / dt = 100a / s CCC 62 CCC t j = 125c i rrm reverse recovery current CCC 2.03 CCC a t j = 25c t on forward turn-on time intrinsic turn-on time is ne g li g ible (turn-on is dominated by ls+ld) conditions v ds = 25v, i d = 168a i d = 168a v gs = 20v v gs = -20v mosfet symbol showing the v ds = 30v conditions v gs = 10v v gs = 0v v ds = 50v ? = 1.0mhz (see fig 5) v gs = 0v, v ds = 0v to 48v (see fig 11) v gs = 0v, v ds = 0v to 48v t j = 25c, i s = 168a, v gs = 0v integral reverse p-n junction diode. conditions v gs = 0v, i d = 250a reference to 25c, i d = 5ma v gs = 10v, i d = 168a v ds = v gs , i d = 250a v ds = 60v, v gs = 0v v ds = 60v, v gs = 0v, t j = 125c i d = 168a r g = 2.7 ? v gs = 10v v dd = 39v i d = 168a, v ds =0v, v gs = 10v ana nc ns pf a ns nc 293 1172 CCC CCC CCC CCC downloaded from: http:///

www.irf.com 3 fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage 0.1 1 10 100 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 15v 10v 8.0v 6.0v 5.0v 4.5v 4.0v bottom 3.5v 60s pulse width tj = 25c 3.5v 2 3 4 5 6 7 v gs , gate-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) t j = 25c t j = 175c v ds = 25v 60s pulse width -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.5 1.0 1.5 2.0 2.5 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 168a v gs = 10v 0 40 80 120 160 200 240 280 q g , total gate charge (nc) 0.0 4.0 8.0 12.0 16.0 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 48v v ds = 30v i d = 168a 0.1 1 10 100 v ds , drain-to-source voltage (v) 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 15v 10v 8.0v 6.0v 5.0v 4.5v 4.0v bottom 3.5v 60s pulse width tj = 175c 3.5v 1 10 100 v ds , drain-to-source voltage (v) 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss downloaded from: http:///

4 www.irf.com fig 8. maximum safe operating area fig 10. drain-to-source breakdown voltage fig 7. typical source-drain diode forward voltage fig 11. typical c oss stored energy fig 9. maximum drain current vs. case temperature fig 12. maximum avalanche energy vs. draincurrent 0.0 0.4 0.8 1.2 1.6 2.0 v sd , source-to-drain voltage (v) 1.0 10 100 1000 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , temperature ( c ) 55 60 65 70 75 80 v ( b r ) d s s , d r a i n - t o - s o u r c e b r e a k d o w n v o l t a g e ( v ) id = 5ma 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 200 400 600 800 1000 1200 1400 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 35a 70a bottom 168a 0 1 02 03 04 05 06 0 v ds, drain-to-source voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 e n e r g y ( j ) 25 50 75 100 125 150 175 t c , case temperature (c) 0 50 100 150 200 250 300 350 i d , d r a i n c u r r e n t ( a ) limited by package 0.1 1 10 100 v ds , drain-to-source voltage (v) 0.1 1 10 100 1000 10000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) operation in this area limited by r ds (on) tc = 25c tj = 175c single pulse 100sec 1msec 10msec dc limited by package downloaded from: http:///

www.irf.com 5 fig 13. maximum effective transient thermal impedance, junction-to-case fig 14. typical avalanche current vs.pulsewidth fig 15. maximum avalanche energy vs. temperature notes on repetitive avalanche curves , figures 14, 15:(for further info, see an-1005 at www.irf.com) 1. avalanche failures assumption: purely a thermal phenomenon and failure occurs at a temperature far inexcess of t jmax . this is validated for every part type. 2. safe operation in avalanche is allowed as long ast jmax is not exceeded. 3. equation below based on circuit and waveforms shown in figures 16a, 16b.4. p d (ave) = average power dissipation per single avalanche pulse. 5. bv = rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. i av = allowable avalanche current. 7. ? t = allowable rise in junction temperature, not to exceed t jmax (assumed as 25c in figure 14, 15).t av = average time in avalanche. d = duty cycle in avalanche = t av f z thjc (d, t av ) = transient thermal resistance, see figures 13) p d (ave) = 1/2 ( 1.3bvi av ) = t/ z thjc i av = 2 t/ [1.3bvz th ] e as (ar) = p d (ave) t av 1e-006 1e-005 0.0001 0.001 0.01 0.1 t 1 , rectangular pulse duration (sec) 0.0001 0.001 0.01 0.1 1 t h e r m a l r e s p o n s e ( z t h j c ) c / w 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc j j 1 1 2 2 3 3 r 1 r 1 r 2 r 2 r 3 r 3 ci i / ri ci= i / ri c 4 4 r 4 r 4 ri (c/w) i (sec) 0.0062 0.0000050.0431 0.000045 0.1462 0.001067 0.2047 0.010195 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 50 100 150 200 250 300 350 e a r , a v a l a n c h e e n e r g y ( m j ) top single pulse bottom 1.0% duty cycle i d = 168a 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 tav (sec) 1 10 100 1000 a v a l a n c h e c u r r e n t ( a ) 0.05 duty cycle = single pulse 0.10 allowed avalanche current vs avalanche pulsewidth, tav, assuming ? j = 25c and tstart = 150c. 0.01 allowed avalanche current vs avalanche pulsewidth, tav, assuming ? tj = 150c and tstart =25c (single pulse) downloaded from: http:///

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fig 16. threshold voltage vs. temperature

-75 -50 -25 0 25 50 75 100 125 150 175 t j , temperature ( c ) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v g s ( t h ) , g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250a i d = 1.0ma i d = 1.0a 0 200 400 600 800 1000 1200 di f /dt (a/s) 0 4 8 12 16 20 i r r ( a ) i f = 112a v r = 51v t j = 25c t j = 125c 0 200 400 600 800 1000 1200 di f /dt (a/s) 0 4 8 12 16 20 i r r ( a ) i f = 168a v r = 51v t j = 25c t j = 125c 0 200 400 600 800 1000 1200 di f /dt (a/s) 0 100 200 300 400 500 600 q r r ( a ) i f = 112a v r = 51v t j = 25c t j = 125c 0 200 400 600 800 1000 1200 di f /dt (a/s) 0 100 200 300 400 500 600 q r r ( a ) i f = 168a v r = 51v t j = 25c t j = 125c downloaded from: http:///

www.irf.com 7 fig 23a. switching time test circuit fig 23b. switching time waveforms fig 22b. unclamped inductive waveforms fig 22a. unclamped inductive test circuit t p v (br)dss i as r g i as 0.01 ? t p d.u.t l v ds + - v dd driver a 15v 20v v gs fig 24a. gate charge test circuit fig 24b. gate charge waveform vds vgs id vgs(th) qgs1 qgs2 qgd qgodr fig 21.
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p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-appliedvoltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period !"#$%#%
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d.u.t. v ds i d i g 3ma v gs .3 f 50k ? .2 f 12v current regulator same type as d.u.t. current sampling resistors + - v ds 90%10% v gs t d(on) t r t d(off) t f ( ) 1 * % 0.1 % &'&& ( + - downloaded from: http:///

8 www.irf.com d 2 pak - 7 pin part marking information d 2 pak (to-263cb) 7 long leads package outline dimensions are shown in milimeters (inches) note: for the most current drawing please refer to ir website at: http://www.irf.com/package/ downloaded from: http:///

www.irf.com 9 d 2 pak - 7 pin tape and reel dimensions are shown in milimeters (inches) data and specifications subject to change without notice. this product has been designed and qualified for the industrial market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . 10/2008 note: for the most current drawing please refer to ir website at: http://www.irf.com/package/ downloaded from: http:///

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